Flash memory is the main stream of nonvolatile memories and is mainly classified into two categories, namely NOR Flash and NAND Flash, wherein NAND Flash is particularly applied for mass data storage. In recent years, with the rise of various portable multimedia storage devices, the market demand for NAND Flash is increased significantly. Therefore, the research and development of the manufacturing process technique is continuously improved for shrinking the device dimension and enhancing the product reliability.
The conventional memory structure includes plane storage units formed on a silicon substrate and the manufacturing process is continuously repeated according to the designed layer number. Because of continuously repeated manufacturing process, the cost is high and cannot be easily reduced. At present, the structure and manufacturing process of the vertical-type nonvolatile memory cell have been developed in order to increase the memory cell density and enhance the integrity of the integrated circuit. Besides, the memory configuration, in which respective twin bits are stored in a memory cell, has advantages of low cost, fast write/read time and high density.
Please refer to FIG. 1, which is a schematic diagram showing a nonvolatile memory cell (which is a vertical-type twin-bit NAND memory cell) of the prior art. The nonvolatile memory cell includes a polysilicon control gate 17 and two polysilicon floating gates 11. Each of the floating gates 11 has a top on which a silicon nitride spacer layer 12 is disposed. An oxide-nitride-oxide (ONO) dielectric layer 16 is disposed between the control gate 17 and each of the floating gates 11. An oxide layer 13 is disposed between the control gate 17 and a silicon substrate 10. And an oxide channel 14 is disposed between the floating gates 11 and the silicon substrate 10.
The method for making the nonvolatile memory cell structured as above mainly includes the following steps. A silicon substrate 10 is provided. At least two polysilicon floating gates 11 serving as spacers are disposed above the silicon substrate 10, wherein each of the floating gates 11 has a top on which a silicon nitride spacer layer 12 is disposed, and a trench having a bottom and plural side surfaces is disposed. An ONO dielectric layer is deposited on the spacer layer 12, at the bottom of the trench and on the plural side surfaces of the trench. Anisotropic etching is performed for leaving a portion 16 of the ONO dielectric layer on the plural side surfaces of the trench. An oxide layer 13 is deposited at the bottom of the trench. A polysilicon control gate 17 is deposited in the trench. And etching back, deposition and polish etc are performed on the polysilicon control gate 17. However, dry etching, performed on ONO dielectric layer mentioned in a step of the above method of the prior art for making the vertical-type twin-bit NAND memory cell, is prone to produce a residual silicon nitride at corners of the plural side surfaces, and a problem that the gate oxide layer 13 of the produced memory cell has a thinner portion can occur. Therefore, the electrical characteristic and stability of the device are influenced.